Synchronous memory technologies implement memory reads and writes based on clock signals. Skew of various signals can result in data stored in memory and read from memory having poor integrity. For example, data that is stored or read can be invalid when sampled at incorrect timing. Skew can result from different loading of the signals. Different impedances of different physical paths for signals, which can be caused by differences in physical path lengths, for example, can result in different delays for the signals. The delays in the signals can cause the skew that can result in invalid data being sampled. Effects of skew can become more pronounced at higher frequency sampling rates. To address skew, synchronous memory technologies can implement calibration processes to offset effects of skew.